Not Applicable
1. Field of the Invention
This invention relates to interference tolerance testing and characterization in a digital signal link. More particularly, the invention concerns a circuit network for injecting test interference signals into a digital signal link for evaluation of the tolerance of the link to extraneous interference and noise. The digital signal link may be a digital circuit, a connection between digital circuits, or any other serial (or parallel) data path.
2. Description of the Prior Art
The tolerance of a digital signal link to interference and noise is often difficult to measure. A major part of the problem is how to inject test interference signals into the link in a precise and controlled manner, without disrupting the normal signal path characteristics. The need for a broad frequency test range adds to the difficulty. Moreover, methods are needed for testing digital signal links carrying either common mode and differential mode signals.
Benefits of characterizing digital signal link interference and noise tolerance include the ability to design more reliable and robust equipment, and the avoidance of system level problems related to cross-talk and electromagnetic (EM) susceptibility. These are often found during late stages of system integration when they are very difficult and expensive to remedy.
Prior art characterizations of digital signal link interference and noise tolerance have been performed qualitatively based on an all-or-nothing, xe2x80x9cgo/no-goxe2x80x9d approach. With these methods, the design margin of the tested link based on its tolerance to extraneous interfering signals is not provided.
A system that allows quantitative (as well as qualitative) measurement of the tolerance of a digital signal link to extraneous signals originating from within the equipment (cross-talk) or which inadvertently couples into the data signal path from outside the equipment, i.e., electromagnetic coupling (EMC), would be desirable. What is required is a test system that inserts interference test signals unobtrusively into the digital signal link to be evaluated, preferably over a broad frequency range, so that the response of the digital signal link to the applied interference may be observed.
A solution to the foregoing problem is provided by a test system that facilitates the efficient characterization of interference and noise tolerance in a digital signal link. Testing may be performed on the elements of any high speed serial (or parallel) data path, including the line driver, the interconnection path elements such as printed wiring board (PWB) traces, vias, connectors and signal cables, and the line receiver. Testing is performed using only passive (linear) components that allow the injection of controlled amounts of an impedance-matched interference signal into the digital signal link with minimal disruption of the normal digital signal path characteristics.
In a first preferred embodiment of the invention, the test system includes a digital data signal generator, a digital data signal receiver, a digital signal link to be tested, and a test interference signal injection (TISI) network connected as part of the digital signal link. The TISI network includes a data signal input port for receiving digital data signals generated by the data signal generator, a data signal output port for providing digital data signals to the data signal receiver, and a controlled-impedance data signal path carrying digital data signals between the data signal input port and the data signal output port. An interference signal input port in the TISI network receives interference signals over a range of frequencies from an interference signal generator. One or more directional couplers within the TISI network directionally couple the interference signals in a controlled fashion into the data signal path, toward either the data signal output or input port, at an impedance that substantially matches the impedance of the digital signal link.
The directional couplers are preferably broadband microwave directional coupling transformers with several decades of bandwidth. Advantageously, the TISI network is configured so that the directional couplers transfer d.c. voltage levels present in the digital data signals through the TISI network while blocking the d.c. voltage levels present in the interference signals. More specifically, the directional coupler ground pins are preferably connected to a plurality of parallel-connected bypass capacitors to provide a floating node that acts as an a.c. ground, thus allowing the d.c. voltage levels of the digital data signals to pass unimpeded through the directional couplers to the data signal output port. A series capacitor is provided at the directional coupler pins receiving the interference signals to block the d.c. levels therein.
The digital signal link may carry either common mode or differential mode digital data signals. There are preferably two directional coupling transformers provided in the TISI network. When common mode interference is to be coupled into the data signal path, common mode interference signals having the same phase and amplitude are applied to both of the coupling transformers. When differential mode interference is to be coupled into the data path, differential mode interference signals having the same amplitude but a 180 degree phase differential are applied to the directional couplers. A phase splitter circuit within the TISI network receives the interference signals from the interference signal input port and selectively provides the common mode interference signals and the differential mode interference signals to the directional couplers. The phase splitter preferably includes a pair of impedance matching transformers, one of which is a non-phase splitting transformer having a grounded end terminal for providing the common mode interference signals, and the other being a phase splitting transformer having a grounded center-tap terminal for providing the differential mode interference signals. A switch-activated radio frequency relay is employed to selectively apply the common mode interference signals and the differential mode interference signals from the impedance matching transformers to the directional coupling transformers.
The digital data signal generator and receiver can be implemented as a bit error rate (BER) generator and a BER receiver, respectively, in order to measure bit error rates as a function of the frequency and signal strength of the applied interference. In addition, one or more monitoring ports can be provided in the test system for connecting signal monitoring equipment at one or more locations in the digital signal link under test to sample digital data signals carried therein. By way of example, a sampling oscilloscope could be connected to a monitoring port in order to observe changes in the digital waveforms as interference is applied.
In a second preferred embodiment of the invention, the data signal generator and the data signal receiver are part of a signal generating and analysis suite. The signal generating and analysis suite communicates with a test board that in turn communicates with a circuit unit under test (UUT). The test board mounts the driver end components of an outbound digital signal link that extends from the test board to the receiver end of the UUT. The test board also mounts the receiver end components of an inbound digital signal link that extends to the test board from the driver end of the UUT. The outbound and inbound digital signal links include appropriate signal carrying media, such as cabling, extending between the test board and the UUT. During interference and noise tolerance testing, the UUT is operated in a loop back mode such that digital test signals carried from the test board to the UUT on the outbound digital signal link are immediately returned from the UUT to the test board on the inbound digital signal link. In this way, useful information can be determined about the driver and receiver ends of the UUT and the digital signal carrying connections thereto.
In a first aspect of the second embodiment, a TISI network is mounted on the test board and adapted to be incorporated into either the outbound digital signal link or the inbound digital signal link. In a second aspect of the second embodiment, the TISI network is mounted on the test board and adapted to be selectively connected to either the outbound digital signal link or the inbound digital signal link. As data signals are driven on the digital signal links, the TISI network is activated to inject varying levels and types of interference into the data signal path.
In the second preferred embodiment, the data signal generator and receiver might respectively include a pattern generator circuit and a logic analyzer circuit, each implementing transistor-transistor logic (TTL) carried on parallel data paths. To convert this parallel data to the serial data format carried on the digital signal link, additional circuit components, including a pattern generator clock circuit, a serial-to-parallel conversion circuit, and a parallel-to-serial signal conversion circuit, may be incorporated on the test board. A clock recovery circuit may also be provided for deriving clock signals from the serial data signals received at the digital signal link receiver. If the digital signal links carry low voltage differential signals (LVDS), the test board may also include PECL-to-LVDS and LVDS-to-PECL signal translation circuits. As in the case of the first preferred embodiment, one or more monitoring ports can be provided in the digital signal links for connecting signal monitoring equipment. Preferably, one pair of monitoring ports is provided between the driver end of the outbound digital signal link and the receiver end of the UUT, and another pair of monitoring ports is provided between the driver end of the UUT and the receiver end of the inbound digital signal link.